1. Field of the Invention
The present invention relates to a capacitor structure. More particularly, the present invention relates to a built-in capacitor structure with an elongated electrode plates to achieve top, bottom, and side cross coupling of the electrode plates, so as to enhance the capacitance.
2. Description of Related Art
In a circuit of modern high-frequency and high-speed electronic system products, e.g. Intel INTEL Pentium-4 CPU circuit substrates, or personal computer motherboards, or mobile phone printed circuit boards, in order to filter various electric noises from the system and stabilize the voltage, several capacitor devices must be added in parallel between a power end and a ground end (e.g. between 5 V and the ground end, or between 3.3 V and the ground end). The capacitor devices are also known as decoupling capacitors. Commonly, the devices functioning as the decoupling capacitor adopt mainly two technologies, namely the discrete component capacitors, e.g. the Surface Mount Technology (SMT) capacitors and the newly developed capacitive substrate provided with decoupling function.
The discrete capacitor has at least the deficiencies that the operating frequency band range is not wide enough, the AC impedance is not low enough, and the system in package cannot be realized, and so on. The current capacitive substrate devices have the defect of a strong via electric parasite effect. Further, the capacitive substrate only has a 2D plane structure. Therefore, this design has the problems of a large area, a great deal of electrical power consumption for the dielectric material of the capacitor, and so on.
Early printed circuit boards usually employed plane substrates of the same dielectric coefficient, e.g. glass fiber cloth (FR4) substrates, which has the disadvantages that the noise inhibition effect is poor at high frequency, and the integration level of the passive components is relatively low. It is improved, for example, in the plane substrate with the inner layer made of different dielectric materials, which is disclosed in U.S. Pat. Nos. 5,079,069 and 5,161,086, so as to enhance the electrical characteristics of the capacitive character among the circuit boards to inhibit the noise. Therefore, the disadvantages of the plane substrate can be reduced. However, as for the modern high-frequency analog and high-speed digital integrated electronic system, it is a double-layer electrode plate occupies areas and compared with the electrode plate of the same area, the side space that can be applied is reduced.
In the CAPACITOR LAMINATE FOR USE IN CAPACITIVE PRINTED CIRCUIT BOARDS AND METHODS OF MANUFACTURE disclosed by the U.S. Pat. No. 5,161,086 assigned to Zycon, published on Nov. 3, 1992, the principle is that the substrate with the same dielectric coefficient is provided on the same plane, and has a conductive metal layer adhered to the upper and lower surfaces to constitute a plane capacitive substrate. The printed circuit board 100 as shown in FIG. 1A has a capacitor laminate structure 110 with two metal layers 112 and 114 and a dielectric layer 116 sandwiched between the two metal layers 112 and 114. Conductive lines 122 and 124 are used to connect to other conductive layer structure, e.g. the conductive layer structure 130 as shown in the figure.
The above structure has the upper side and lower side connected by vias, and when being laminated with other conventional printed circuit board, the structure can provide a function as a capacitor to inhibit the noise. Referring to FIG. 1B, in addition to the above application, the electrode plate can also adopt a multi-layer design. In addition to the former structure, a capacitor laminate 140 structure is further added, which includes two metal layers 142 and 144 and a dielectric layer 146 sandwiched between the two metal layers 142 and 144. The leads 122 and 124 are used to connect to the other conductive layer structure of the other layer, e.g. the conductive layer structure 130 as shown in the figure. However, the multi-layer structure may cause an increase of the length of the vias and affect the electric effect.
Additionally, referring to FIG. 1C, it is a microscopic structure of a single electrode plate. As known from the microscopic structure, the disadvantage lies in that the single electrode plate cannot exert the advantage of edge coupling, and the area occupied is relatively large. Further, with the design of the vias, not only is the inductive effect enhanced and the applied frequency range reduced, but also the area of the underlayer is occupied. The design is directed to the application to the ground decoupling capacitor, and does not have significant effect on the application to the capacitors connected in series.
Further, in the CAPACITOR FORMED WITH PRINTED CIRCUIT BOARDS disclosed by the U.S. Pat. No. 5,972,053 assigned to International Business Machine, published on Oct. 26, 1999, a design of electrode plate is provided, which can also adopt a multi-layer design as shown in FIG. 2A. As shown in the drawing, in the printed circuit board 200, two resistors 210 and 220 are sandwiched between the dielectric layers 202, 204, and 206, and connected to the outer conductive layer by the vias 232, 234, and 236. However, the multi-layer structure may cause an increase of the length of the vias and affect the electrical effect. FIG. 2B is a microscopic structure of a single electrode plate. The design of the electrode plate has a disadvantage that the single electrode plate cannot exert the advantage of the edge coupling, and the area occupied is relatively large. Further, with the design of the vias, not only is the inductive effect enhanced and the applied frequency range reduced, but also the area of the underlayer is occupied.
In another conventional technology, a high-density capacitor is achieved by increasing the surface area of the structure in the process of the semiconductor integrated circuit. However, the effect is limited. Actually, the stereo-crossing structure can be used to increase the surface area. For example, in the THREE DIMENTIONAL POLYSILICON CAPACITOR FOR HIGH DENSITY INTEGRATED CIRCUIT APPLICATIONS disclosed by the U.S. Pat. No. 5,744,853, published on Apr. 28, 1998, a design of the stereo-crossing structure being used for increasing the surface area is provided, so as to achieve the requirement of the high-density capacitor. Referring to FIG. 3, the triple-layer structure of a patterned polysilicon layer 310, an insulator layer 320, and another patterned polysilicon layer 330 forms a capacitor with a stereo-crossing structure.